Ph.D. Dissertation on "Low power digital design using energy recovery Adiabatic logic"
The term ‘adiabatic’ is borrowed from the subject of thermodynamics and has been used in digital system design since 1994. Many researchers working in the domain of VLSI and circuit theory have contributed to this energy recovery technique in last few years. Based on the exhaustive literature survey of research papers in this area, we had defined our research objectives as;
1. Compare various quasi-adiabatic logic styles already reported in the literature for power consumption and energy-delay product using one common platform of 180 nm technology since the reported results from literature are on adiabatic circuits developed at different times and hence of different technologies. 2. Select and hypothesize a suitable quasi-adiabatic MOS logic style for a typical digital circuit and experimentally prove that it is superior to conventional optimized CMOS logic styles. 3. Propose and demonstrate a way to reduce leakage power dissipation in quasi-adiabatic logic and develop a boundary circuit which would act as interface between adiabatic logic and CMOS logic.
The research work in this direction was carried out in phases. Initially, we proved the energy recovery principle and established the energy measurement technique. Then we compared the performances of selected quasi-adiabatic logic styles and prepared the research platform, based on statistical and analytical study, to design a new quasi-adiabatic logic style. We have proposed a new quasiadiabatic logic style called ‘PAL2NSM’ and proved that it is superior quasiadiabatic logic style to PAL and PAL2N already published in the literature This is a major contribution. The term ‘PAL2NSM’ is coined by us indicating modification to stand-by mode (SM) in PAL2N style. In the next phase, we tested the new quasi-adiabatic logic style against noise and jitter. Since ‘noise and jitter testing’ of quasi-adiabatic circuit has not been reported in any literature, this work of ours also is a significant contribution. During this research work, the need of additional circuit to dynamically minimize the leakage power in quasi-adiabatic circuit and a boundary circuit between adiabatic and CMOS circuit was realized. We successfully designed, implemented and tested these two circuits. Both the circuits can be deployed with any quasi-adiabatic logic style and therefore the designs of these two circuits are also significant contributions made in quasi-adiabatic circuit theory.
